Most current logic computations and logic operations are performed by logic circuits whose fundamental elements are logic gates. In certain applications unrelated to high performance applications, ROM (Read only Memory) based design has been employed. For example, ROM based design has been employed in Field Programmable Gate Array (FPGA) architectures, where basic logic gates like NAND, and NOR have been implemented. In addition, a similar approach has also been used to generate series of functions like logarithmic numbers and sinusoidal functions. However, these ROM based designs are mostly used for simple logic functions or operations, such as logic functions or operations with a low logic depth (logic depth being related to the maximum number of series-arranged processing elements in a logic circuit). One major reason for slower operation and higher energy consumption in such ROM based design in FPGA architectures, as well as other devices, is the use this approach for achieving reconfigurability. For this purpose, mainly basic gates are implemented using very small ROM structures (typically, 4 to 16 bit), which requires an increased number of transistors as compared to a conventional CMOS gate. Moreover, a ROM based design in general results in a larger area than its counterpart with conventional logic gates. Similarly, in the context of implementing series logic functions using ROM based designs, this typically involves the employment of large ROM sizes, which result in large delays (e.g., accessing the memory), increased area usage, and increased power usage as compared to designed with conventional logic gates.
Therefore, existing memory based designs for logic computations and/or logic operations do not relate to high-performance applications. There remains a continued need for improvements in high performance logic computations and logic operations.